1. Field of the Invention
The invention relates generally to a damascene method of fabricating metal interconnections on integrated circuits and, more particularly, to a damascene method that incorporates the use of a release layer to remove residual liner and metal particles that can cause electrical shorts between the metal interconnections.
2. Description of the Related Art
The damascene process is a process in which metal interconnect lines are delineated and isolated in dielectrics by means of chemical mechanical polishing (CMP). A dual damascene process is a similar process in which both metal interconnect lines and vias (i.e., conductor-filled channels) are delineated, such that the conductor material used to form the metal interconnect lines is continuous with the conductor of the vias. Time Dependent Dielectric Breakdown (TDDB) is a technique commonly used to test the reliability of dielectrics in metal oxide semiconductor (MOS) device technologies, e.g., to test the reliability of the dielectric material used to isolate metal interconnect lines. Often times TDDB fails occur in the metal interconnections. For example, short circuits may be caused by residual metal (e.g., copper (Cu)) or liner materials (e.g., titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), etc.) that is not removed from the dielectric material by the CMP during the damascene or dual damascene process. One known solution to removing the residual liner and/or metal material is further polishing of the dielectric material and the metal interconnect lines. However, increased polishing can remove too much of the metal and, thus, can cause an increase in resistance. Therefore, an improved damascene and dual damascene process is needed to improve device reliability without forfeiting line resistance.